Gate recess engineering of pseudomorphic In/sub 0.30/GaAs/GaAs HEMTs - Electronics Letters

and a 15011s time constant. These pulses are applied on the collector of the simulated devices, while their emitter and substrate are grounded. The thermal boundary condition is considered to be a constant temperature of 300K at the bottom of the simulation domain which corresponds to the substrate electrode. Fig. 2 shows the calculated transient voltage responses of the two transistors submitted to a low stress level (peak current I, = S d p ) and to a high stress level (I, = 1 5 d p n ) . This figure shows that initially the voltage across the device increases up to the triggering level (points A and A’, Fig. 2). The simulated values of the triggering voltage of the two devices are in good agreement with the experimentally measured values (Table 1). In fact, the triggering voltages under transient conditions are lower than under static conditions owing to capacitive effects and the existence of displacements currents. Accordingly, the devices enter in snap-back and the voltage decreases up to the sustaining level (points B and B’, Fig. 2). When this occurs, the greatest part of the discharge current flows laterally from the collector to the emitter under the field oxide (PBL, see Fig. la), while the conductivity of the base region is significantly modulated [6], which leads to a decrease in the resistance of the discharge path. However, the applied current still increases, since its maximum value is attained at lOns (points C and C‘, Fig. 2), also causing the terminal voltage to increase. Subsequently, the current decays exponentially and when it reaches the value for which the snap-back condition is not satisfied anymore, the terminal voltage goes back to the triggering voltage of the device (points E and E’, Fig. 2). Fig. 2 also shows that at high stress level the terminal voltage of the CPW device increases after the current has reached each peak value, and that it decreases in the case of the ODPW device (points D and D’, Fig. 2). This is a thermal effect and can be attributed to the decrease of the mobility as well as to the increase of the avalanche voltage at high temperatures. The calculated maximum temperature transients for the different stress levels of the examined devices (Fig. 3) show that at high stress level the maximum temperature in the CPW device is considerably higher than in the ODPW device. This fact is probably the cause of the observed different failure levels of the tested transistors.